1. Field of the Invention
The present invention relates to a method for calibrating a timing clock. More particularly, the present invention relates to a timing clock calibration method for calibrating a timing clock generating section that generates a timing clock indicative of a timing at which a test signal is to be fed to a device under test.
2. Related Art
A test apparatus for testing a semiconductor device includes a timing clock generating section that generates a timing clock for causing generation of a given waveform, that is a fundamental function of the test apparatus, a shift clock generating section that generates a shift clock for linearizing the timing clock, and a timing clock and shift clock phase comparing section that compares a phase of the timing clock and that of the shift clock with each other.
The timing clock generating section includes a variable timing delaying section formed by a variable delaying circuit, and a linearizing memory that stores a setting value for selecting a delay path in the variable delay circuit, and can generate a given timing clock by switching the delay path in real time. The shift clock generating section includes a phase synchronization circuit and can generate a shift clock having a given phase. Based on the assumption that the shift clock has a highly accurate phase linearity, the phase of the timing clock is matched to the phase of the shift clock while the timing clock and shift clock phase comparing section compares the timing clock and the shift clock with each other. In this manner, the phase of the timing clock is linearized and the setting value to be stored in the linearizing memory is set.
The description of a document referring to conventional art is omitted here because the inventor does not find such a document at this point in time.
With recent increase of an operation speed of a semiconductor device, generation of the timing clock with a high degree of accuracy has been required in a test apparatus. However, a conventional test apparatus has a problem that it cannot linearize the phase of the timing clock with a high degree of accuracy in a case where the shift clock contains a small phase linear error because linearization of the phase of the timing clock is performed by using the shift clock as a reference based on assumption that the shift clock generated by the shift clock generating section has highly accurate phase linearity.